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ISL6255, ISL6255A
Data Sheet June 17, 2005 FN9203.1
Highly Integrated Battery Charger with Automatic Power Source Selector for Notebook Computers
The ISL6255, ISL6255A is a highly integrated battery charger controller for Li-Ion/Li-Ion polymer batteries. High Efficiency is achieved by a synchronous buck topology and the use of a MOSFET, instead of a diode, for selecting power from the adapter or battery. The low side MOSFET emulates a diode at light loads to improve the light load efficiency and prevent system bus boosting. The constant output voltage can be selected for 2, 3 and 4 series Li-Ion cells with 0.5% accuracy over temperature. It can also be programmed between 4.2V+5%/cell and 4.2V-5%/cell to optimize battery capacity. When supplying the load and battery charger simultaneously, the input current limit for the AC adapter is programmable to within 3% accuracy to avoid overloading the AC adapter, and to allow the system to make efficient use of available adapter power for charging. It also has a wide range of programmable charging current. The ISL6255, ISL6255A provides outputs that are used to monitor the current drawn from the AC adapter, and monitor for the presence of an AC adapter. The ISL6255, ISL6255A automatically transitions from regulating current mode to regulating voltage mode. ISL6255, ISL6255A has a feature for automatic power source selection by switching to the battery when the AC adapter is removed or switching to the AC adapter when the AC adapter is available. It also provides a DC adapter monitor to support aircraft power applications with the option of no battery charging.
Features
* 0.5% Charge Voltage Accuracy (-10C to 100C) * 3% Accurate Input Current Limit * 3% Accurate Battery Charge Current Limit * 25% Accurate Battery Trickle Charge Current Limit (ISL6255A) * Programmable Charge Current Limit, Adapter Current Limit and Charge Voltage * Fixed 300kHz PWM Synchronous Buck Controller with Diode Emulation at Light Load * Output for Current Drawn from AC Adapter * AC Adapter Present Indicator * Fast Input Current Limit Response * Input Voltage Range 7V to 25V * Support 2, 3 and 4 Cells Battery Pack * Up to 17.64V Battery-Voltage Set Point * Control Adapter Power Source Select MOSFET * Thermal Shutdown * Aircraft Power Capable * DC Adapter Present Indicator * Battery Discharge MOSFET Control * Less than 10A Battery Leakage Current * Support Pulse Charging * Charge Any Battery Chemistry: Li-Ion, NiCd, NiMH, etc * Pb-Free Plus Anneal Available (RoHS Compliant)
Ordering Information
PART NUMBER ISL6255HRZ (Notes 1, 2) ISL6255HAZ (Notes 1, 2) ISL6255AHRZ (Notes 1, 2) ISL6255AHAZ (Notes 1, 2)
NOTES:
TEMP RANGE (C) -10 to 100 -10 to 100 -10 to 100 -10 to 100
PACKAGE 28 Ld 5x5 QFN (Pb-free) 28 Ld QSOP (Pb-free) 28 Ld 5x5 QFN (Pb-free) 28 Ld QSOP (Pb-free)
PKG. DWG. # L28.5x5 M28.15 L28.5x5 M28.15
Applications
* Notebook, Desknote and Sub-notebook Computers * Personal Digital Assistant
1. Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
2. Add "-T" for Tape and Reel.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL6255, ISL6255A Pinouts
ISL6255, ISL6255A (28 LD QFN) TOP VIEW
DCPRN ACPRN DCSET ACSET CSON DCIN VDD DCIN VDD ACSET EN CELLS ICOMP VCOMP ICM VREF CHLIM 1 2 3 4 5 6 7 8 ACLIM 9 VADJ 10 GND 11 PGND 12 LGATE 13 VDDP 14 BOOT 21 20 19 18 17 16 15 CSOP CSIN CSIP SGATE BGATE PHASE UGATE ACLIM VADJ GND DCSET EN CELLS ICOMP VCOMP ICM VREF CHLIM
ISL6255, ISL6255A (28 LD QSOP) TOP VIEW
1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 DCPRN ACPRN CSON CSOP CSIN CSIP SGATE BGATE PHASE UGATE BOOT VDDP LGATE PGND
28
27
26
25
24
23
22
2
FN9203.1 June 17, 2005
ISL6255, ISL6255A
Absolute Maximum Ratings
DCIN, CSIP, CSON to GND. . . . . . . . . . . . . . . . . . . . . -0.3V to +28V CSIP-CSIN, CSOP-CSON . . . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V CSIP-SGATE, CSIP-BGATE . . . . . . . . . . . . . . . . . . . . . -0.3V to 16V PHASE to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -7V to 30V BOOT to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +35V BOOT-PHASE, VDD-GND, VDDP-PGND ACPRN and DCPRN to GND . . . . . . . . . . . . . . . . . . . . -0.3V to 7V ACSET and DCSET to GND (Note 3) . . . . . . . . -0.3V to VDD+0.3V ICM, ICOMP, VCOMP to GND. . . . . . . . . . . . . . -0.3V to VDD+0.3V ACLIM, CHLIM, VREF, CELLS to GND . . . . . . . -0.3V to VDD+0.3V EN, VADJ, PGND to GND . . . . . . . . . . . . . . . . . -0.3V to VDD+0.3V UGATE. . . . . . . . . . . . . . . . . . . . . . . . . PHASE-0.3V to BOOT+0.3V LGATE . . . . . . . . . . . . . . . . . . . . . . . . . . PGND-0.3V to VDDP+0.3V
Thermal Information
Thermal Resistance JA (C/W) JC (C/W) QFN Package (Notes 4, 5). . . . . . . . . . 39 9.5 QSOP Package (Note 4) . . . . . . . . . . . 80 NA ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Level 2 Junction Temperature Range. . . . . . . . . . . . . . . . . .-10C to +150C Operating Temperature Range . . . . . . . . . . . . . . . .-10C to +100C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C Lead Temperature (soldering, 10s) . . . . . . . . . . . . . . . . . . . . +300C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES: 3. When the voltage across ACSET and DCSET is below 0V, the current through ACSET and DCSET should be limited to less than 1mA. 4. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. See Tech Brief TB379. 5. For JC, the "case temp" location is the center of the exposed metal pad on the package underside.
Electrical Specifications
DCIN=CSIP=CSIN=18V, CSOP=CSON=12V, ACSET=DCSET=1.5V, ACLIM=VREF, VADJ=Floating, EN=VDD=5V, BOOT-PHASE=5.0V, GND=PGND=0V, CVDD=1F, IVDD=0mA, TA=-10C to +100C, TJ 125C, unless otherwise noted. TEST CONDITIONS MIN TYP MAX UNITS
PARAMETER SUPPLY AND BIAS REGULATOR DCIN Input Voltage Range DCIN Quiescent Current Battery Leakage Current (Note 6) VDD Output Voltage/Regulation VDD Undervoltage Lockout Trip Point
7 EN=VDD or GND, 7V DCIN 25V DCIN=0, no load 7V DCIN 25V, 0 IVDD 30mA VDD Rising Hysteresis 4.925 4.0 200 2.365 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 1.4 3 5.075 4.4 250 2.39
25 3 10 5.225 4.6 400 2.415 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5
V mA A V V mV V % % % % % % % % %
Reference Output Voltage VREF Battery Charge Voltage Accuracy
0 IVREF 300A CSON=16.8V, CELLS=VDD, VADJ=Float CSON=12.6V, CELLS=GND, VADJ=Float CSON=8.4V, CELLS=Float, VADJ=Float CSON=17.64V, CELLS=VDD, VADJ=VREF CSON=13.23V, CELLS=GND, VADJ=VREF CSON=8.82V, CELLS=Float, VADJ=VREF CSON=15.96V, CELLS=VDD, VADJ=GND CSON=11.97V, CELLS=GND, VADJ=GND CSON=7.98V, CELLS=Float, VADJ=GND
TRIP POINTS ACSET Threshold ACSET Input Bias Current Hysteresis ACSET Input Bias Current ACSET Input Bias Current DCSET Threshold ACSET 1.26V ACSET < 1.26V 1.24 2.2 2.2 -1 1.24 1.26 3.4 3.4 0 1.26 1.28 4.4 4.4 1 1.28 V A A A V
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FN9203.1 June 17, 2005
ISL6255, ISL6255A
Electrical Specifications
DCIN=CSIP=CSIN=18V, CSOP=CSON=12V, ACSET=DCSET=1.5V, ACLIM=VREF, VADJ=Floating, EN=VDD=5V, BOOT-PHASE=5.0V, GND=PGND=0V, CVDD=1F, IVDD=0mA, TA=-10C to +100C, TJ 125C, unless otherwise noted. (Continued) TEST CONDITIONS MIN 2.2 DCSET 1.26V DCSET < 1.26V 2.2 -1 TYP 3.4 3.4 0 MAX 4.4 4.4 1 UNITS A A A
PARAMETER DCSET Input Bias Current Hysteresis DCSET Input Bias Current DCSET Input Bias Current OSCILLATOR Frequency PWM Ramp Voltage (peak-peak) CSIP=18V CSIP=11V SYNCHRONOUS BUCK REGULATOR Maximum Duty Cycle UGATE Pull-up Resistance UGATE Source Current UGATE Pull-down Resistance UGATE Sink Current LGATE Pull-up Resistance LGATE Source Current LGATE Pull-down Resistance LGATE Sink Current
245
300 1.6 1
355
kHz V V
97 BOOT-PHASE=5V, 500mA source current BOOT-PHASE=5V, BOOT-UGATE=2.5V BOOT-PHASE=5V, 500mA sink current BOOT-PHASE=5V, UGATE-PHASE=2.5V VDDP-PGND=5V, 500mA source current VDDP-PGND=5V, VDDP-LGATE=2.5V VDDP-PGND=5V, 500mA sink current VDDP-PGND=5V, LGATE=2.5V
99 1.8 1.0 1.0 1.8 1.8 1.0 1.0 1.8
99.6 3.0
% A
1.8
A
3.0
A
1.8
A
CHARGING CURRENT SENSING AMPLIFIER Input Common-Mode Range Input Offset Voltage Input Bias Current at CSOP Input Bias Current at CSON CHLIM Input Voltage Range CSOP to CSON Full-Scale Current Sense Voltage ISL6255: CHLIM=3.3V ISL6255A: CHLIM=3.3V ISL6255: CHLIM=2.0V ISL6255A: CHLIM=2.0V ISL6255: CHLIM=0.2V ISL6255A: CHLIM=0.2V CHLIM Input Bias Current CHLIM Power-Down Mode Threshold Voltage CHLIM Power-Down Mode Hysteresis Voltage ADAPTER CURRENT SENSING AMPLIFIER Input Common-Mode Range Input Offset Voltage Input Bias Current at CSIP & CSIN Combined Input Bias Current at CSIN Guarantee by design CSIP=CSIN=25V 0 < CSIN < DCIN, Guaranteed by design 7 -2 100 0.10 25 2 130 1 V mV A A CHLIM=GND or 3.3V, DCIN=0V CHLIM rising Guaranteed by design 0 < CSOP < 18V 0 < CSON < 18V 0 157 160 95 97 5.0 7.5 -1 80 15 88 25 165 165 100 100 10 10 0 -2.5 0 0.25 75 18 2.5 2 100 3.6 173 170 105 103 15.0 12.5 1 95 40 V mV A A V mV mV mV mV mV mV A mV mV
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FN9203.1 June 17, 2005
ISL6255, ISL6255A
Electrical Specifications
DCIN=CSIP=CSIN=18V, CSOP=CSON=12V, ACSET=DCSET=1.5V, ACLIM=VREF, VADJ=Floating, EN=VDD=5V, BOOT-PHASE=5.0V, GND=PGND=0V, CVDD=1F, IVDD=0mA, TA=-10C to +100C, TJ 125C, unless otherwise noted. (Continued) TEST CONDITIONS MIN TYP MAX UNITS
PARAMETER ADAPTER CURRENT LIMIT THRESHOLD CSIP to CSIN Full-Scale Current Sense Voltage
ACLIM=VREF ACLIM=Float ACLIM=GND
97 72 47 10 -20
100 75 50 16 -16
103 78 53 20 -10
mV mV mV A A
ACLIM Input Bias Current
ACLIM= VREF ACLIM=GND
VOLTAGE REGULATION ERROR AMPLIFIER Error Amplifier Transconductance from CSON to VCOMP CELLS=VDD 30 A/V
CURRENT REGULATION ERROR AMPLIFIER Charging Current Error Amplifier Transconductance Adapter Current Error Amplifier Transconductance BATTERY CELL SELECTOR CELLS Input Voltage for 4 Cell Select CELLS Input Voltage for 3 Cell Select CELLS Input Voltage for 2 Cell Select MOSFET DRIVER BGATE Pull-up Current BGATE Pull-down Current CSIP-BGATE Voltage High CSIP-BGATE Voltage Low DCIN-CSON Threshold for CSIP-BGATE Going High DCIN-CSON Threshold Hysteresis SGATE Pull-up Current SGATE Pull-down Current CSIP-SGATE Voltage High CSIP-SGATE Voltage Low CSIP-CSIN Threshold for CSIP-SGATE Going High CSIP-CSIN Threshold Hysteresis LOGIC INTERFACE EN Input Voltage Range EN Threshold Voltage Rising Falling Hysteresis EN Input Bias Current ACPRN Sink Current EN=2.5V ACPRN=0.4V 0 1.030 0.985 30 1.8 3 1.06 1.000 60 2.0 8 VDD 1.100 1.025 90 2.2 11 V V V mV A mA CSIP-SGATE=3V CSIP-SGATE=5V DCIN=12V, CSON Rising CSIP-BGATE=3V CSIP-BGATE=5V 10 2.7 8 50 -100 250 7 50 8 -50 2.5 1 30 4.0 9.6 0 0 300 12 160 9 0 5.5 2 45 5.0 11 50 100 400 15 370 11 50 10 5 mA mA V mV mV mV mA A V mV mV mV 2.1 4.3 2 4.2 V V V 50 50 A/V A/V
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FN9203.1 June 17, 2005
ISL6255, ISL6255A
Electrical Specifications
DCIN=CSIP=CSIN=18V, CSOP=CSON=12V, ACSET=DCSET=1.5V, ACLIM=VREF, VADJ=Floating, EN=VDD=5V, BOOT-PHASE=5.0V, GND=PGND=0V, CVDD=1F, IVDD=0mA, TA=-10C to +100C, TJ 125C, unless otherwise noted. (Continued) TEST CONDITIONS ACPRN=5V DCPRN=0.4V DCPRN=5V CSIP-CSIN=100mV CSIP-CSIN=75mV CSIP-CSIN=50mV Thermal Shutdown Temperature Thermal Shutdown Temperature Hysteresis NOTE: 6. This is the sum of currents in these pins (CSIP, CSIN, BGATE, BOOT, UGATE, PHASE, CSOP, CSON) all tied to 16.8V. No current in pins EN, ACSET, DCSET, VADJ, CELLS, ACLIM, CHLIM. MIN -0.5 3 -0.5 -3 -4 -5 0 0 0 150 25 8 TYP MAX 0.5 11 0.5 +3 +4 +5 UNITS A mA A % % % C C
PARAMETER ACPRN Leakage Current DCPRN Sink Current DCPRN Leakage Current ICM Output Accuracy (Vicm=19.9 x (Vcsip-Vcsin))
Typical Operating Performance
0.6
VDD LOAD REGULATION ACCURACY (%) VDD=5.075V EN=0
DCIN=20V, 4S2P Li-Battery, TA=25C, unless otherwise noted.
0.1
VREF LOAD REGULATION ACCURACY (%) VREF=2.390V
0.3
0.08
0.06
0
0.04
-0.3
0.02
-0.6 0 8 16 24 32 40
LOAD CURRENT (mA)
0 0 100 200 300 400
LOAD CURRENT (A)
FIGURE 1. VDD LOAD REGULATION
FIGURE 2. VREF LOAD REGULATION
10 Test 9 8 | ICM ACCURACY | (%) 7 6
EFFICIENCY (%)
1 0 .9 6 0 .9 2 0 .8 8 0 .8 4 0 .8 0 .76 0 0 .5 1 1.5 2 2.5 3 3 .5 4
CHARGE CURRENT (A) VCSON=12.6V (3 CELLS) VCSON=16.8V 4 CELLS VCSON=8.4V 2 CELLS
5 4 3 2 1 0 10 20 30 40 50 60 70 80 90 100
CSIP-CSIN (mV)
FIGURE 3. ICM ACCURACY vs AC ADAPTER CURRENT
FIGURE 4. SYSTEM EFFICIENCY vs CHARGE CURRENT
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FN9203.1 June 17, 2005
ISL6255, ISL6255A Typical Operating Performance
DCIN=20V, 4S2P Li-Battery, TA=25C, unless otherwise noted. (Continued)
LOAD CURRENT 5A/div ADAPTER CURRENT 5A/div CHARGE CURRENT 2A/div LOAD STEP: 0-4A CHARGE CURRENT: 3A AC ADAPTER CURRENT LIMIT: 5.15A
DCIN 10V/div
ACSET 1V/div DCSET 1V/div
DCPRN 5V/div ACPRN 5V/div
BATTERY VOLTAGE 2V/div
FIGURE 5. AC & DC ADAPTER DETECTION
FIGURE 6. LOAD TRANSIENT RESPONSE
CSON 5V/div EN 5V/div
INDUCTOR CURRENT 2A/div
BATTERY INSERTION BATTERY REMOVAL
INDUCTOR CURRENT 2A/div CHARGE CURRENT 2A/div
CSON 10V/div
VCOMP ICOMP
VCOMP 2V/div ICOMP 2V/div
FIGURE 7. CHARGER ENABLE & SHUTDOWN
FIGURE 8. BATTERY INSERTION AND REMOVAL
CHLIM=0.2V CSON=8V
PHASE 10V/div
PHASE 10V/div INDUCTOR CURRENT 1A/div
UGATE 2V/div
UGATE 5V/div
LGATE 2V/div
FIGURE 9. AC ADAPTER REMOVAL
FIGURE 10. AC ADAPTER INSERTION
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FN9203.1 June 17, 2005
ISL6255, ISL6255A Typical Operating Performance
DCIN=20V, 4S2P Li-Battery, TA=25C, unless otherwise noted. (Continued)
ADAPTER REMOVAL
SGATE-CSIP 2V/div
BGATE-CSIP 2V/div SYSTEM BUS VOLTAGE 10V/div
SYSTEM BUS VOLTAGE 10V/div BGATE-CSIP 2V/div INDUCTOR CURRENT 2A/div
SGATE-CSIP 2V/div INDUCTOR CURRENT 2A/div
ADAPTER INSERTION
FIGURE 11. SWITCHING WAVEFORMS AT DIODE EMULATION
FIGURE 12. SWITCHING WAVEFORMS IN CC MODE
CHARGE CURRENT 1A/div
CHLIM 1V/div
FIGURE 13. TRICKLE TO FULL-SCALE CHARGING
Functional Pin Descriptions
BOOT
Connect BOOT to a 0.1F ceramic capacitor to PHASE pin and connect to the cathode of the bootstrap schottky diode.
PHASE
The Phase connection pin connects to the high side MOSFET source, output inductor, and low side MOSFET drain.
UGATE
UGATE is the high side MOSFET gate drive output.
CSOP/CSON
CSOP/CSON is the battery charging current sensing positive/negative input. The differential voltage across CSOP and CSON is used to sense the battery charging current, and is compared with the charging current limit threshold to regulate the charging current. The CSON pin is also used as the battery feedback voltage to perform voltage regulation.
SGATE
SGATE is the AC adapter power source select output. The SGATE pin drives an external P-MOSFET used to switch to AC adapter as the system power source.
BGATE
Battery power source select output. This pin drives an external P-channel MOSFET used to switch the battery as the system power source. When the voltage at CSON pin is higher than the AC adapter output voltage at DCIN, BGATE is driven to low and selects the battery as the power source.
CSIP/CSIN
CSIP/CSIN is the AC adapter current sensing positive/negative input. The differential voltage across CSIP and CSIN is used to sense the AC adapter current, and is compared with the AC adapter current limit to regulate the AC adapter current.
LGATE
LGATE is the low side MOSFET gate drive output; swing between 0V and VDDP. 8
GND
GND is an analog ground.
FN9203.1 June 17, 2005
ISL6255, ISL6255A
DCIN
The DCIN pin is the input of the internal 5V LDO. Connect it to the AC adapter output. Connect DCIN to a 0.1F ceramic capacitor.
VDDP
VDDP is the supply voltage for the low-side MOSFET gate driver. Connect a 4.7 resistor to VDD and a 1F ceramic capacitor to power ground.
ACSET
ACSET is an AC adapter detection input. Connect to a resistor divider from the adapter input.
ICOMP
ICOMP is a current loop error amplifier output.
VCOMP
VCOMP is a voltage loop amplifier output.
ACPRN
ACPRN is an AC adapter present open drain output. ACPRN is active low when ACSET is higher than typically 1.26V, and active high when ACSET is lower than typically 1.26V.
CELLS
This pin is used to select the battery voltage. CELLS=VDD for a 4S battery pack, CELLS=GND for a 3S battery pack, CELLS=Float for a 2S battery pack.
DCSET
DCSET is a lower voltage adapter detection input (like aircraft power 15V). This allows to power the system, but not to charge the battery.
VADJ
VADJ adjusts battery regulation voltage. VADJ=VREF for 4.2V+5%/cell; VADJ=Floating for 4.2V/cell; VADJ=GND for 4.2V-5%/cell. Connect to a resistor divider to program the desired battery cell voltage between 4.2V-5% and 4.2V+5%.
DCPRN
DCPRN is a DC adapter present open drain output. DCPRN is active low when DCSET is higher than typically 1.26V, and active high when DCSET is lower than typically 1.26V.
CHLIM
CHLIM is the battery charge current limit set pin.CHLIM input voltage range is 0.1V to 3.6V. When CHLIM=3.3V, the set point for CSOP-CSON is 165mV. The charger shuts down if CHLIM is forced below 88mV.
EN
EN is the Charge Enable input. Connecting EN to high enables the charge control function, connecting EN to low disables charging functions. Use with a thermistor to detect a hot battery and suspend charging.
ACLIM
ACLIM is the adapter current limit set pin. ACLIM=VREF for 100mV, ACLIM=Floating for 75mV, and ACLIM=GND for 50mV. Connect a resistor divider to program the adapter current limit threshold between 50mV and 100mV.
ICM
ICM is the adapter current output. The output of this pin produces a voltage proportional to the adapter current.
VREF
VREF is a 2.39V reference output pin. It is internally compensated. Do not connect a decoupling capacitor.
PGND
PGND is the power ground. Connect PGND to the source of the low side MOSFET.
VDD
VDD is an internal LDO output to supply IC analog circuit. Connect a 1F ceramic capacitor to ground.
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FN9203.1 June 17, 2005
ISL6255, ISL6255A
SGATE
CSIP
CSIN
DCSET +
DCPRN
+
ACSET ACPRN
+ + 1.27V Adapter Adapter Current Limit Set Current Limit Set gm3 + Min Min Min Current Current Buffer Buffer Min Min Voltage Voltage Buffer + 0.25 VCA2 Voltage Selector gm2 -PWM +
ACLIM
ICOMP
2.1V
+ gm1 -
VCOMP
VADJ
CELLS VDD
V CA2 PGND 20 CA2 --+ + + + 1.065V
VREF
Reference Reference
-
GND
CSON
CSOP
CHLIM
FIGURE 14. FUNCTIONAL BLOCK DIAGRAM
10
CSON -+ + BGATE DCIN DCIN LDO Regulator LDO VDD BOOT UGATE PHASE VDDP LGATE EN
FN9203.1 June 17, 2005
ICM
+ +
CA1 X19.9 19.9 CA1
1.26V
+
ISL6255, ISL6255A
AC ADAPTER R8 130k 1% R9 10.2k 1% C7 1 1F 3.3V R5 100k C6:6.8nF ICOMP ICOMP R6: 10k C5:10nF VCOMP VCOMP FLOATING 4.2V/CELL CHARGE ENABLE VADJ VADJ EN EN ACLIM ACLIM VREF VREF VREF R12 2.6A CHARGE LIMIT 20k 1% 253mA Trickle Charge CHLIM CHLIM R13 1.87k 1% R11 130k 1% Q6 GND PHASE PHASE LGATE Q2 PGND PGND CSOP CSOP C3 1 1F CSON CSON CELLS ICM R7: 100 C11 3300pF VDD 4 CELLS C10 10F 10 R4 2.2 2.2 R10 4.7 4.7 VDD VDD C9 1 1F ACPRN ACPRN BOOT BOOT D2 UGATE UGATE C4 0.1 0.1F Q1 To Host Controller VDD Q5 C8 0.1 0.1F CSON SGATE CSIP C2 0.1 0.1F CSIN CSIN BGATE R3 18 18 VDDP C1:10 F Q4 R2 20m 20m Q3
DCIN DCIN ACSET ACSET
ISL6255 ISL6255 ISL6255A ISL6255A ISL6255A VDDP VDDP
SYSTEM LOAD
D1 Optional
L 10H
R1 40m 40m BAT+ Battery Pack BAT-
TRICKLE CHARGE
FIGURE 15. ISL6255, ISL6255A TYPICAL APPLICATION CIRCUIT WITH FIXED CHARGING PARAMETERS
11
FN9203.1 June 17, 2005
ISL6255, ISL6255A
ADAPTER VDD Q5 C8 0.1 0.1 Q3 CSON
R8 130k 1% R14 100k 1% R9 10.2k 1%
DCIN DCIN ACSET ACSET DCSET DCSET
SGATE SGATE CSIP CSIP C2 0.1 0.1F R2 20m 20m
R15 11.5k 1%
SYSTEM LOAD
C7 1F C9 1F 1 R10 4.7 4.7
CSIN ISL6255 CSIN ISL6255 ISL6255 ISL6255A ISL6255A ISL6255A BGATE BGATE VDDP VDDP BOOT BOOT VDD VDD UGATE UGATE ACPRN ACPRN DCPRN DCPRN PHASE PHASE LGATE LGATE Q2 CHLIM CHLIM EN EN PGND PGND CSOP CSOP C3 1F 1 CSON CSON ACLIM ACLIM CELLS CELLS VREF VREF VADJ VADJ ICOMP ICOMP GND GND VCOMP VCOMP R6 10k C5 10nF FLOATING 4.2V/CELL BATTERY Pack GND 3 CELLS C10 10 10F R4 2.2 2.2 R1 40m 40m BAT+ D2 Q1 C4 0.1F 0.1 R3: 18 Q4 VDDP C1:10 C1:10F
VCC DIGITAL INPUT DIGITAL INPUT D/A OUTPUT OUTPUT R7: 100 A/D INPUT HOST C11 VREF 3300pF 5.15A INPUT CURRENT LIMIT C6 6.8nF R16 100k R5 100k
D1 Optional
L 10H 10
ICM ICM
R11,R12 R13: 10K AVDD/VREF
SCL SDL A/D INPUT GND
SCL SDL TEMP BAT-
FIGURE 16. ISL6255, ISL6255A TYPICAL APPLICATION CIRCUIT WITH P CONTROL AND AIRCRAFT POWER SUPPORT
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FN9203.1 June 17, 2005
ISL6255, ISL6255A Theory of Operation
Introduction
The ISL6255, ISL6255A includes all of the functions necessary to charge 2 to 4 cell Li-Ion and Li-polymer batteries. A high efficiency synchronous buck converter is used to control the charging voltage and charging current up to 10A. The ISL6255, ISL6255A has input current limiting and analog inputs for setting the charge current and charge voltage; CHLIM inputs are used to control charge current and VADJ inputs are used to control charge voltage. The ISL6255, ISL6255A charges the battery with constant charge current, set by CHLIM input, until the battery voltage rises up to a programmed charge voltage set by VADJ input; then the charger begins to operate at a constant voltage charge mode. The charger also drives an adapter isolation p-channel MOSFET to efficiently switch in the adapter supply. ISL6255, ISL6255A is a complete power source selection controller for single battery systems and also aircraft power applications. It drives a battery selector p-channel MOSFET to efficiently select between a single battery and the adapter. It controls the battery discharging MOSFET and switches to the battery when the AC adapter is removed, or, switches to the AC adapter when the AC adapter is inserted for single battery system. The EN input allows shutdown of the charger through a command from a micro-controller. It also uses EN to safely shutdown the charger when the battery is in extremely hot conditions. The amount of adapter current is reported on the ICM output. Figure 14 shows the IC functional block diagram. The synchronous buck converter uses external N-channel MOSFETs to convert the input voltage to the required charging current and charging voltage. Figure 15 shows the ISL6255, ISL6255A typical application circuit with charging current and charging voltage fixed at specific values. The typical application circuit shown in Figure 16 shows the ISL6255, ISL6255A typical application circuit which uses a micro-controller to adjust the charging current set by CHLIM input for aircraft power applications. The voltage at CHLIM and the value of R1 sets the charging current. The DC/DC converter generates the control signals to drive two external N-channel MOSFETs to regulate the voltage and current set by the ACLIM, CHLIM, VADJ and CELLS inputs. The ISL6255, ISL6255A features a voltage regulation loop (VCOMP) and two current regulation loops (ICOMP). The VCOMP voltage regulation loop monitors CSON to ensure that its voltage never exceeds the voltage and regulates the battery charge voltage set by VADJ. The ICOMP current regulation loops regulate the battery charging current delivered to the battery to ensure that it never exceeds the charging current limit set by CHLIM; and the ICOMP current regulation loops also regulate the input current drawn from the AC adapter to ensure that it never exceeds the input current limit set by ACLIM, and to prevent a system crash and AC adapter overload.
PWM Control
The ISL6255, ISL6255A employs a fixed frequency PWM current mode control architecture with a feed-forward function. The feed-forward function maintains a constant modulator gain of 11 to achieve fast line regulation as the buck input voltage changes. When the battery charge voltage approaches the input voltage, the DC/DC converter operates in dropout mode, where there is a timer to prevent the frequency from dropping into the audible frequency range. It can achieve duty cycle of up to 99.6%. To prevent boosting of the system bus voltage, the battery charger operates in standard-buck mode when CSOPCSON drops below 4.25mV. Once in standard-buck mode, hysteresis does not allow synchronous operation of the DC/DC converter until CSOP-CSON rises above 12.5mV. An adaptive gate drive scheme is used to control the dead time between two switches. The dead time control circuit monitors the LGATE output and prevents the upper side MOSFET from turning on until LGATE is fully off, preventing cross-conduction and shoot-through. In order for the dead time circuit to work properly, there must be a low resistance, low inductance path from the LGATE driver to MOSFET gate, and from the source of MOSFET to PGND. The external Schottky diode is between the VDDP pin and BOOT pin to keep the bootstrap capacitor charged.
Setting the Battery Regulation Voltage
The ISL6255, ISL6255A uses a high-accuracy trimmed band-gap voltage reference to regulate the battery charging voltage. The VADJ input adjusts the charger output voltage, and the VADJ control voltage can vary from 0 to VREF, providing a 10% adjustment range (from 4.2V-5% to 4.2V+5%) on CSON regulation voltage. An overall voltage accuracy of better than 0.5% is achieved. The per-cell battery termination voltage is a function of the battery chemistry. Consult the battery manufacturers to determine this voltage. * Float VADJ to set the battery voltage VCSON=4.2V x number of the cells, * Connect VADJ to VREF to set 4.41V x number of cells, * Connect VADJ to ground to set 3.99V x number of the cells. So, the maximum battery voltage of 17.6V can be achieved. Note that other battery charge voltages can be set by connecting a resistor divider from VREF to ground. The resistor divider should be sized to draw no more than 100A from VREF; or connect a low impedance voltage source like the D/A converter in the micro-controller. The programmed
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battery voltage per cell can be determined by the following equation: VCELL = 0.175 VVADJ + 3.99 V Connect CELLS as shown in Table 1 to charge 2, 3 or 4 Li+ cells. When charging other cell chemistries, use CELLS to select an output voltage range for the charger. The internal error amplifier gm1 maintains voltage regulation. The voltage error amplifier is compensated at VCOMP. The component values shown in Figure 16 provide suitable performance for most applications. Individual compensation of the voltage regulation and current-regulation loops allows for optimal compensation.
TABLE 1. CELL NUMBER PROGRAMMING CELLS VDD GND Float CELL NUMBER 4 3 2
bias current and less influence on current-sense accuracy and voltage regulation accuracy.
Setting the Input Current Limit
The total input current from an AC adapter, or other DC source, is a function of the system supply current and the battery-charging current. The input current regulator limits the input current by reducing the charging current, when the input current exceeds the input current limit set point. System current normally fluctuates as portions of the system are powered up or down. Without input current regulation, the source must be able to supply the maximum system current and the maximum charger input current simultaneously. By using the input current limiter, the current capability of the AC adapter can be lowered, reducing system cost. The ISL6255, ISL6255A limits the battery charge current when the input current-limit threshold is exceeded, ensuring the battery charger does not load down the AC adapter voltage. This constant input current regulation allows the adapter to fully power the system and prevent the AC adapter from overloading and crashing the system bus. An internal amplifier gm3 compares the voltage between CSIP and CSIN to the input current limit threshold voltage set by ACLIM. Connect ACLIM to REF, Float and GND for the full-scale input current limit threshold voltage of 100mV, 75mV and 50mV, respectively, or use a resistor divider from VREF to ground to set the input current limit as the following equation 1 0.05 VACLIM + 0.050 IINPUT = R2 VREF When choosing the current sense resistor, note that the voltage drop across this resistor causes further power dissipation, reducing efficiency. The AC adapter current sense accuracy is very important. Use a 1% tolerance current-sense resistor. The highest accuracy of 3% is achieved with 100mV current-sense threshold voltage for ACLIM=VREF, but it has the highest power dissipation. For example, it has 400mW power dissipation for rated 4A AC adapter and 1W sensing resistor may have to be used. 4% and 6% accuracy can be achieved with 75mV and 50mV current-sense threshold voltage for ACLIM=Floating and ACLIM=GND, respectively. A low pass filter is suggested to eliminate the switching noise. Connect the resistor to CSIN pin instead of CSIP pin because CSIN pin has lower bias current and less influence on the current-sense accuracy.
Setting the Battery Charge Current Limit
The CHLIM input sets the maximum charging current. The current set by the current sense-resistor connects between CSOP and CSON. The full-scale differential voltage between CSOP and CSON is 165mV for CHLIM=3.3V, so the maximum charging current is 4.125A for a 40m sensing resistor. Other battery charge current-sense threshold values can be set by connecting a resistor divider from VREF or 3.3V to ground, or by connecting a low impedance voltage source like a D/A converter in the micro-controller. The charge current limit threshold is given by:
165mV V CHLIM I CHG = ------------------- --------------------3.3V R1
To set the trickle charge current for the dumb charger, a resistor in series with a switch Q6 (Figure 15) controlled by the micro-controller is connected from CHLIM pin to ground. The trickle charge current is determined by:
165mV V CHLIM ,trickle I CHG = ------------------- --------------------------------------3.3V R1
When the CHLIM voltage is below 88mV (typical), it will disable the battery charge. When choosing the current sensing resistor, note that the voltage drop across the sensing resistor causes further power dissipation, reducing efficiency. However, adjusting CHLIM voltage to reduce the voltage across the current sense resistor R1 will degrade accuracy due to the smaller signal to the input of the current sense amplifier. There is a trade-off between accuracy and power dissipation. A low pass filter is recommended to eliminate switching noise. Connect the resistor to the CSOP pin instead of the CSON pin, as the CSOP pin has lower
AC Adapter Detection
Connect the AC adapter voltage through a resistor divider to ACSET to detect when AC power is available, as shown in Figure 15. ACPRN is an open-drain output and is high when
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ACSET is less than Vth,rise, and active low when ACSET is above Vth,fall. Vth,rise and Vth,fall are given by:
R Vth ,rise = 8 + 1 * VACSET R 9
and ICOMP are pulled to ground. The ICM, ACPRN and DCPRN outputs continue to function. EN can be driven by a thermistor to allow automatic shutdown of the ISL6255, ISL6255A when the battery pack is hot. Often a NTC thermistor is included inside the battery pack to measure its temperature. When connected to the charger, the thermistor forms a voltage divider with a resistive pull-up to the VREF. The threshold voltage of EN is 1.0V with 60mV hysteresis. The thermistor can be selected to have a resistance vs temperature characteristic that abruptly decreases above a critical temperature. This arrangement automatically shuts down the ISL6255, ISL6255A when the battery pack is above a critical temperature. Another method for inhibiting charging is to force CHLIM below 85mV (Typ.).
R Vth,fall = 8 + 1 * V ACSET - I hys R8 R 9
Where Ihys is the ACSET input bias current hysteresis and VACSET = 1.24V (min), 1.26V (typ.) and 1.28V (max.). The hysteresis is IhysR8, where Ihys=2.2A (min.), 3.4A (typ.) and 4.4A (max.)
DC Adapter Detection
Connect the DC adapter voltage like aircraft power through a resistor divider to DCSET to detect when DC power is available, as shown in Figure 16. DCPRN is an open-drain output and is high when DCSET is less than Vth,rise, and active low when DCSET is above Vth,fall. Vth,rise and Vth,fall are given by:
R 14 V th, rise = --------- + 1 * V DCSET R 15
Supply Isolation
If the voltage across the adapter sense resistor R2 is typically greater than 8.5mV, the p-channel MOSFET controlled by SGATE is turned on reducing the power dissipation. If the voltage across the adapter sense resistor R2 is less than 5.5mV, SGATE turns off the p-channel MOSFET isolating the adapter from the system bus.
R 14 V th, fall = --------- + 1 * V DCSET - I hys R 14 R 15
Battery Power Source Selection and Aircraft Power Application
The battery voltage is monitored by CSON. If the battery voltage measured on CSON is less than the adapter voltage measured on DCIN, then the p-channel MOSFET controlled by BGATE turns off. If it is greater, then BGATE turns on the battery discharge p-channel MOSFET to minimize the power loss. In the meantime, it also disables charging function and turns off the AC adapter isolation p-channel MOSFET controlled by SGATE. If designing for airplane power, DCSET is tied to a resistor divider sensing the adapter voltage. When a user is plugged into the 15V airplane supply and the battery voltage is lower than 15V, the MOSFET driven by BGATE (See Figure 16) is turned off and keeps the battery from supplying the system bus. The comparator looking at CSON and DCIN has 300mV of hysteresis to avoid chattering. It supports only 3S and 2S for DC aircraft power applications.
Where Ihys is the DCSET input bias current hysteresis and VDCSET=1.24V (min), 1.26V (typ.) and 1.28V (max.). The hysteresis is IhysR14, where Ihys=2.2A (min.), 3.4A (typ.) and 4.4A (max.)
Current Measurement
Use ICM to monitor the input current being sensed across CSIP and CSIN. The output voltage range is 0 to 2.5V. The voltage of ICM is proportional to the voltage drop across CSIP and CSIN, and is given by the following equation:
ICM = 19.9 * I INPUT * R 2
where IINPUT is the DC current drawn from the AC adapter. ICM has 3% accuracy. It is recommended to have an RC filter at the ICM output for minimizing the switching noise.
LDO Regulator
VDD provides a 5.0V supply voltage from the internal LDO regulator from DCIN and can deliver up to 30mA of current. The MOSFET drivers are powered by VDDP, which must be connected to VDDP as shown in Figure 15. VDDP connects to VDD through an external low pass filter. Bypass VDDP and VDD with a 1F capacitor.
Short Circuit Protection and 0V Battery Charging
Since the battery charger will regulate the charge current to the limit set by CHLIM, it automatically has short circuit protection and is able to provide the charge current to wake up an extremely discharged battery.
Over Temperature Protection
If the die temp exceeds 150C, it stops charging. Once the die temp drops below 1250C, charging will start up again.
Shutdown
The ISL6255, ISL6255A features a low-power shutdown mode. Driving EN low shuts down the ISL6255, ISL6255A. In shutdown, the DC/DC converter is disabled, and VCOMP
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ISL6255, ISL6255A Application Information
The following battery charger design refers to the typical application circuit in Figure 15, where typical battery configuration of 4S2P is used. This section describes how to select the external components including the inductor, input and output capacitors, switching MOSFETs, and current sensing resistors. 10V (2.5V/Cell) and the maximum battery voltage of 16.8V. The maximum RMS value of the output ripple current occurs at the duty cycle of 0.5 and is expressed as:
I RMS =
VIN ,MAX 4 12 L f s
Inductor Selection
The inductor selection has trade-offs between cost, size and efficiency. For example, the lower the inductance, the smaller the size, but ripple current is higher. This also results in higher AC losses in the magnetic core and the windings, which decrease the system efficiency. On the other hand, the higher inductance results in lower ripple current and smaller output filter capacitors, but it has higher DCR (DC resistance of the inductor) loss, and has slower transient response. So, the practical inductor design is based on the inductor ripple current being (15-20)% of the maximum operating DC current at maximum input voltage. The required inductance can be calculated from:
L= VIN ,MAX - VBAT
For VIN,MAX=19V, L=10H, and fs=300kHz, the maximum RMS current is 0.46A. A typical 10F ceramic capacitor is a good choice to absorb this current and also has very small size. The tantalum capacitor has a known failure mechanism when subjected to high surge current. EMI considerations usually make it desirable to minimize ripple current in the battery leads. Beads may be added in series with the battery pack to increase the battery impedance at 300kHz switching frequency. Switching ripple current splits between the battery and the output capacitor depending on the ESR of the output capacitor and battery impedance. If the ESR of the output capacitor is 10m and battery impedance is raised to 2 with a bead, then only 0.5% of the ripple current will flow in the battery.
IL
VBAT VIN ,MAX fs
MOSFET Selection
The Notebook battery charger synchronous buck converter has the input voltage from the AC adapter output. The maximum AC adapter output voltage does not exceed 25V. Therefore, 30V logic MOSFET should be used. The high side MOSFET must be able to dissipate the conduction losses plus the switching losses. For the battery charger application, the input voltage of the synchronous buck converter is equal to the AC adapter output voltage, which is relatively constant. The maximum efficiency is achieved by selecting a high side MOSFET that has the conduction losses equal to the switching losses. Ensure that ISL6255, ISL6255A LGATE gate driver can supply sufficient gate current to prevent it from conduction, which is due to the injected current into the drain-to-source parasitic capacitor (Miller capacitor Cgd), and caused by the voltage rising rate at phase node at the time instant of the high-side MOSFET turning on; otherwise, cross-conduction problems may occur. Reasonably slowing turn-on speed of the highside MOSFET by connecting a resistor between the BOOT pin and gate drive supply source, and the high sink current capability of the low-side MOSFET gate driver help reduce the possibility of cross-conduction. For the high-side MOSFET, the worst-case conduction losses occur at the minimum input voltage:
Where VIN,MAX, VBAT, and fs are the maximum input voltage, battery voltage and switching frequency, respectively. The inductor ripple current I is found from:
I L = 30% I BAT,MAX
where the maximum peak-to-peak ripple current is 30% of the maximum charge current is used. For VIN,MAX=19V, VBAT=16.8V, IBAT,MAX=2.6A, and fs=300kHz, the calculated inductance is 8.3H. Choosing the closest standard value gives L=10H. Ferrite cores are often the best choice since they are optimized at 300kHz to 600kHz operation with low core loss. The core must be large enough not to saturate at the peak inductor current IPeak:
I Peak = I BAT ,MAX + 1 IL 2
Output Capacitor Selection
The output capacitor in parallel with the battery is used to absorb the high frequency switching ripple current and smooth the output voltage. The RMS value of the output ripple current Irms is given by:
IRMS = VIN ,MAX 12 L fs D (1 - D )
where the duty cycle D is the ratio of the output voltage (battery voltage) over the input voltage for continuous conduction mode which is typical operation for the battery charger. During the battery charge period, the output voltage varies from its initial battery voltage to the rated battery voltage. So, the duty cycle change can be in the range of between 0.5 and 0.88 for the minimum battery voltage of
PQ1,Conduction =
VOUT 2 I BAT R DSON VIN
The optimum efficiency occurs when the switching losses equal the conduction losses. However, it is difficult to calculate the switching losses in the high-side MOSFET since it must allow for difficult-to-quantify factors that influence the turn-on and turn-off times. These factors
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include the MOSFET internal gate resistance, gate charge, threshold voltage, stray inductance, pull-up and pull-down resistance of the gate driver. The following switching loss calculation provides a rough estimate.
PQ1,Switching = Qgd Qgd 1 1 + VIN ILP fs + QrrVIN fs VIN ILV fs 2 Ig ,source 2 Ig ,sin k
Where IGATE is the total gate drive current and should be less than 24mA. Substituting IGATE=24mA and fs=300kHz into the previous equation yields that the total gate charge should be less than 80nC. Therefore, the ISL6255, ISL6255A easily drives the battery charge current up to 8A.
Input Capacitor Selection
The input capacitor absorbs the ripple current from the synchronous buck converter, which is given by:
Irms = IBAT VOUT (VIN - VOUT ) VIN
Where Qgd: drain-to-gate charge, Qrr: total reverse recovery charge of the body-diode in low side MOSFET, ILV: inductor valley current, ILP: Inductor peak current, Ig,sink and Ig,source are the peak gate-drive source/sink current of Q1, respectively. To achieve low switching losses, it requires low drain-to-gate charge Qgd. Generally, the lower the drain-to-gate charge, the higher the on-resistance. Therefore, there is a trade-off between the on-resistance and drain-to-gate charge. Good MOSFET selection is based on the Figure of Merit (FOM), which is a product of the total gate charge and onresistance. Usually, the smaller the value of FOM, the higher the efficiency for the same application. For the low-side MOSFET, the worst-case power dissipation occurs at minimum battery voltage and maximum input voltage:
This RMS ripple current must be smaller than the rated RMS current in the capacitor datasheet. Non-tantalum chemistries (ceramic, aluminum, or OSCON) are preferred due to their resistance to power-up surge currents when the AC adapter is plugged into the battery charger. For Notebook battery charger applications, it is recommend that ceramic capacitors or polymer capacitors from Sanyo be used due to their small size and reasonable cost. Table 2 shows the component lists for the typical application circuit in Figure 15.
TABLE 2. COMPONENT LIST PARTS C1, C10 PART NUMBERS AND MANUFACTURER 10F/25V ceramic capacitor, Taiyo Yuden TMK325 MJ106MY X5R (3.2x2.5x1.9mm)
PQ2
V = 1 - OUT VIN
2 I BAT R DSON
Choose a low-side MOSFET that has the lowest possible on-resistance with a moderate-sized package like the SO-8 and is reasonably priced. The switching losses are not an issue for the low side MOSFET because it operates at zerovoltage-switching. Choose a Schottky diode in parallel with low-side MOSFET Q2 with a forward voltage drop low enough to prevent the low-side MOSFET Q2 body-diode from turning on during the dead time. This also reduces the power loss in the high-side MOSFET associated with the reverse recovery of the lowside MOSFET Q2 body diode. As a general rule, select a diode with DC current rating equal to one-third of the load current. One option is to choose a combined MOSFET with the Schottky diode in a single package. The integrated packages may work better in practice because there is less stray inductance due to a short connection. This Schottky diode is optional and may be removed if efficiency loss can be tolerated. In addition, ensure that the required total gate drive current for the selected MOSFETs should be less than 24mA. So, the total gate charge for the high-side and low-side MOSFETs is limited by the following equation:
C2, C4, C8 0.1F/50V ceramic capacitor C3, C7, C9 1F/10V ceramic capacitor, Taiyo Yuden LMK212BJ105MG C5 C6 C11 D1 D2 L Q1, Q2 Q3, Q4 Q5 Q6 R1 R2 R3 R4 R5 R6 R7 R8, R11 10nF ceramic capacitor 6.8nF ceramic capacitor 3300pF ceramic capacitor 30V/3A Schottky diode, EC31QS03L (optional) 100mA/30V Schottky Diode, Central Semiconductor 10H/3.8A/26m, Sumida, CDRH104R-100 30V/35m, FDS6912A, Fairchild -30V/30m, SI4835BDY, Siliconix Signal P-channel MOSFET, NDS352AP Signal N-channel MOSFET, 2N7002 40m, 1%, LRC-LR2512-01-R040-F, IRC 20m, 1%, LRC-LR2010-01-R020-F, IRC 18, 5%, (0805) 2.2, 5%, (0805) 100k, 5%, (0805) 10K, 5%, (0805) 100, 5%, (0805) 130K, 1%, (0805)
QGATE
I GATE fs
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TABLE 2. COMPONENT LIST (Continued) PARTS R9 R10 R12 R13 PART NUMBERS AND MANUFACTURER 10.2k, 1%, (0805) 4.7, 5%, (0805) 20k, 1%, (0805) 1.87k, 1%, (0805)
Transfer function F2(S) from control to inductor current is:
S 1+ z Vin iL = F2 (S ) = 1 Ro + RL S 2 , where z . d S Ro Co + +1 2 oQ p
o
Current loop gain Ti(S) is expressed as the following equation:
Ti ( S ) = RT Fm F2 (S )H e (S )
Loop Compensation Design
ISL6255, ISL6255A uses a constant frequency current mode control architecture to achieve fast loop transient response. Accurate current sensing resistors in series with the output inductor is used to regulate the charge current, and the sensed current signal is injected into the voltage loop to achieve current mode control to simplify the loop compensation design. The inductor is not considered as a state variable for current mode control and the system becomes a single order system. It is much easier to design a compensator to stabilize the voltage loop than voltage mode control. Figure 17 shows the small signal model of the synchronous buck regulator.
where RT is the trans-resistance in current loop. RT is usually equal to the product of the current sensing resistance of the current amplifier. For ISL6255, ISL6255A, RT=20R1. The voltage gain with open current loop is:
Tv ( S ) = KFm F1 (S )Av (S )
Where K = FB , VFB is the feedback voltage of the voltage Vo error amplifier. The Voltage loop gain with current loop closed is given by:
Lv ( S ) = Tv (S ) 1 + Ti (S )
V
PWM Comparator Gain Fm:
The PWM comparator gain Fm for peak current mode control is given by:
If Ti(S)>>1, then it can be simplified as follows:
R + RL V Lv ( S ) = FB o Vo RT 1+
Fm =
d v comp
=
1 VPWM
esr Av (S )
S
S
1+
p
H e (S )
p
1 RoCo
Where VPWM is the peak-peak voltage of the PWM ramp signal.
Current Sampling Transfer Function He(S):
In current loop, the current signal is sampled every switching cycle. It has the following transfer function:
He (S ) = S2
2 n
From the above equation, it is shown that the system is a single order system, which has a single pole located at p before the half switching frequency. Therefore, simple type II compensator can be easily used to stabilize the system. Figure 17 shows the voltage loop compensator, and its transfer function is expressed as follows
in i
v in
IL d
+
S
nQn
+1
2
iL
L
where Qn and n are given by Qn = - , n= fs, respectively.
vo
Rc Ro Co
1:D
Vind
+
Power Stage Transfer Functions
Transfer function F1(S) from control to output voltage is:
v F1 (S ) = o = Vin d S2 1+ S
+
RT
esr
d
Ti(S) K
S + +1 2 o oQ p 1 LC o
Fm Tv(S)
v comp
Where esr =
1 Co , Q p Ro , o = Rc Co L
+
He(S) -Av(S)
FIGURE 17. SMALL SIGNAL MODEL OF SYNCHRONOUS BUCK REGULATOR
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Vo
PCB Layout Considerations
Power and Signal Layers Placement on the PCB
As a general rule, power layers should be close together, either on the top or bottom of the board, with signal layers on the opposite side of the board. As an example, layer arrangement on a 4-layer board is shown below: 1. Top Layer: signal lines, or half board for signal lines and the other half board for power lines 2. Signal Ground 3. Power Layers: Power Ground 4. Bottom Layer: Power MOSFET, Inductors and other Power traces Separate the power voltage and current flowing path from the control and logic level signal path. The controller IC will stay on the signal layer, which is isolated by the signal ground to the power signal traces.
VFB VREF
+ gm
VCOMP
R1 C1
FIGURE 18. VOLTAGE LOOP COMPENSATOR
Av (S ) =
v comp v FB
1+ = gm
S
cz
SC1
1 , where cz = R1C1
Compensator design goal: * High DC gain * Loop bandwidth fc: * Gain margin: >10dB * Phase margin: 40 The compensator design procedure is as follows: 1. Put compensator zero at
1 1 - fs 5 20
Component Placement
The power MOSFET should be close to the IC so that the gate drive signal, the LGATE, UGATE, PHASE, and BOOT, traces can be short. Place the components in such a way that the area under the IC has less noise traces with high dv/dt and di/dt, such as gate signals and phase node signals.
Signal Ground and Power Ground Connection
At minimum, a reasonably large area of copper, which will shield other noise couplings through the IC, should be used as signal ground beneath the IC. The best tie-point between the signal ground and the power ground is at the negative side of the output capacitor on each side, where there is little noise; a noisy trace beneath the IC is not recommended.
cz = (1 - 3 )
1 RoCo
2. Put one compensator pole at zero frequency to achieve high DC gain, and put another compensator pole at either esr zero frequency or half switching frequency, whichever is lower. The loop gain Tv(S) at cross over frequency of fc has unity gain. Therefore, the compensator resistance R1 is determined by:
R1 = 2 fcVo C o RT g mVFB
GND and VDD Pin
At least one high quality ceramic decoupling cap should be used to cross these two pins. The decoupling cap can be put close to the IC.
LGATE Pin
This is the gate drive signal for the bottom MOSFET of the buck converter. The signal going through this trace has both high dv/dt and high di/dt, and the peak charging and discharging current is very high. These two traces should be short, wide, and away from other traces. There should be no other traces in parallel with these traces on any layer.
where gm is the trans-conductance of the voltage loop error amplifier. Compensator capacitor C1 is then given by:
C1 = 1 R1 cz
Example: Vin=20V, Vo=16.8V, Io=2.6A, fs=300kHz, Co=10F/10m, L=10H, gm=250s, RT=0.2, VFB=2.1V, VPWM=VIN/11, fc=25kHz, then compensator resistance R1=10k. Put the compensator zero at 1.5kHz. The compensator capacitor C1 is C1=9.2nF. Therefore, choose voltage loop compensator: R1=10K, C1=10nF.
PGND Pin
PGND pin should be laid out to the negative side of the relevant output cap with separate traces.The negative side of the output capacitor must be close to the source node of the bottom MOSFET. This trace is the return path of LGATE.
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PHASE Pin
This trace should be short, and positioned away from other weak signal traces. This node has a very high dv/dt with a voltage swing from the input voltage to ground. No trace should be in parallel with it. This trace is also the return path for UGATE. Connect this pin to the high-side MOSFET source.
DCIN Pin
This pin connects to AC adapter output voltage, and should be less noise sensitive.
Copper Size for the Phase Node
The capacitance of PHASE should be kept very low to minimize ringing. It would be best to limit the size of the PHASE node copper in strict accordance with the current and thermal management of the application.
UGATE Pin
This pin has a square shape waveform with high dv/dt. It provides the gate drive current to charge and discharge the top MOSFET with high di/dt. This trace should be wide, short, and away from other traces similar to the LGATE.
Identify the Power and Signal Ground
The input and output capacitors of the converters, the source terminal of the bottom switching MOSFET PGND should connect to the power ground. The other components should connect to signal ground. Signal and power ground are tied together at one point.
BOOT Pin
This pin's di/dt is as high as the UGATE; therefore, this trace should be as short as possible.
Clamping Capacitor for Switching MOSFET
It is recommended that ceramic caps be used closely connected to the drain of the high-side MOSFET, and the source of the low-side MOSFET. This capacitor reduces the noise and the power loss of the MOSFET.
CSOP, CSON Pins
The current sense resistor connects to the CSON and the CSOP pins through a low pass filter. The CSON pin is also used as the battery voltage feedback. The traces should be away from the high dv/dt and di/di pins like PHASE, BOOT pins. In general, the current sense resistor should be close to the IC. Other layout arrangements should be adjusted accordingly.
EN Pin
This pin stays high at enable mode and low at idle mode and is relatively robust. Enable signals should refer to the signal ground.
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FN9203.1 June 17, 2005
ISL6255, ISL6255A Quad Flat No-Lead Plastic Package (QFN) Micro Lead Frame Plastic Package (MLFP)
2X 0.15 C A A 9 D1 D1/2 6 INDEX AREA N 1 2 3 E1/2 E1 9 2X 0.15 C B 2X 0.15 C A 4X C 0.08 C SEATING PLANE SIDE VIEW NX b 4X P D2 (DATUM B) 4X P 1 (DATUM A) 6 INDEX AREA NX L Ne 8 (Nd-1)Xe REF. BOTTOM VIEW A1 NX b 5 2 3 E2 7 E2/2 8 (Ne-1)Xe REF. D2 2N 5 0.10 M C A B 7 8 NX k A3 A1 0 TOP VIEW A2 A / / 0.10 C B E/2 E 2X 0.15 C B D D/2
L28.5x5
28 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (COMPLIANT TO JEDEC MO-220VHHD-1 ISSUE I) MILLIMETERS SYMBOL A A1 A2 A3 b D D1 D2 E E1 E2 e k L 0.20 0.50 2.95 2.95 0.18 MIN 0.80 NOMINAL 0.90 0.02 0.65 0.20 REF 0.25 5.00 BSC 4.75 BSC 3.10 5.00 BSC 4.75 BSC 3.10 0.50 BSC 0.60 28 7 7 0.60 12 0.75 3.25 3.25 0.30 MAX 1.00 0.05 1.00 NOTES 9 9 5,8 9 7,8 9 7,8 8 2 3 3 9 9 Rev. 1 11/04 NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals. 3. Nd and Ne refer to the number of terminals on each D and E. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389.
9
N Nd Ne P
9 CORNER OPTION 4X
C L
SECTION "C-C" C L
9. Features and dimensions A2, A3, D1, E1, P & are present when Anvil singulation method is used and not present for saw singulation.
L1 e 10 L
L1 e CC
10
L
TERMINAL TIP FOR ODD TERMINAL/SIDE FOR EVEN TERMINAL/SIDE
21
FN9203.1 June 17, 2005
ISL6255, ISL6255A Shrink Small Outline Plastic Packages (SSOP) Quarter Size Outline Plastic Packages (QSOP)
N INDEX AREA H E -B1 2 3 SEATING PLANE -AD -CA 0.25 0.010 h x 45 L GAUGE PLANE 0.25(0.010) M BM
M28.15
28 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE (0.150" WIDE BODY) INCHES SYMBOL MIN MAX MILLIMETERS MIN MAX NOTES
A A1 A2 B C D
A2 C 0.10(0.004) C AM BS
0.053 0.004 0.008 0.007 0.386 0.150 0.228 0.0099 0.016 28 0
0.069 0.010 0.061 0.012 0.010 0.394 0.157 0.244 0.0196 0.050 8
1.35 0.10 0.20 0.18 9.81 3.81 5.80 0.26 0.41 28 0
1.75 0.25 1.54 0.30 0.25 10.00 3.98 6.19 0.49 1.27 8
9 3 4 5 6 7 Rev. 1 6/04
A1
e
B 0.17(0.007) M
E e H h L N
0.025 BSC
0.635 BSC
NOTES: 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension "B" does not include dambar protrusion. Allowable dambar protrusion shall be 0.10mm (0.004 inch) total in excess of "B" dimension at maximum material condition. 10. Controlling dimension: INCHES. Converted millimeter dimensions are not necessarily exact.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
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FN9203.1 June 17, 2005

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